? semiconductor components industries, llc, 2013 may, 2013 ? rev. 0 1 publication order number: NCP51190/d NCP51190 1.5a ddr memory termination regulator the NCP51190 is a simple, cost ? effective, high ? speed linear regulator designed to generate the v tt termination voltage rail for ddr ? i, ddr ? ii and ddr ? iii memory. the regulator is capable of actively sourcing or sinking up to 1.5 a for ddr ? i, or up to 0.5 a for ddr ? ii / ? iii while regulating the output voltage to within 30 mv. the output termination voltage is tightly regulated to track v tt = (v ddq / 2) over the entire current range. the NCP51190 incorporates a high ? speed differential amplifier to provide ultra ? fast response to line and load transients. other features include extremely low initial offset voltage, excellent load regulation, source/sink soft ? start and on ? chip thermal shut ? down protection. the NCP51190 features the power ? saving suspend to ram (str) function which will tri ? state the regulator output and lower the quiescent current drawn when the /ss pin is pulled low. the NCP51190 is available in a dfn8 package. features ? generate ddr memory termination voltage (v tt ) ? for ddr ? i, ddr ? ii, ddr ? iii source / sink currents ? supports ddr ? i to 1.5 a, ddr ? ii, ddr ? iii to 0.5 a (peak) ? integrated power mosfets with thermal protection ? stable with 10 f ceramic v tt capacitor ? high accuracy output voltage at full ? load ? minimal external component count ? shutdown for standby or suspend to ram (str) mode ? built ? in soft start ? these are pb ? free devices appications ? desktop pc?s, notebooks, and workstations ? graphics card ddr memory termination ? set top boxes, digital tv?s, printers ? embedded systems ? active bus termination marking diagram http://onsemi.com dfn8 mn suffix case 506aa device package shipping ? ordering information dfn8 (pb ? free) 3000 / tape & reel NCP51190mntag pin connection ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 1 a5m 1 a5 = specific device code m = date code = pb ? free device (note: microdot may be in either location)
NCP51190 http://onsemi.com 2 1.5 a, ddr ? i / ? ii / ? iii termination regulator figure 1. typical application schematic pin function description ? NCP51190 pin number pin name pin function 1 pv cc the pv cc pin provides the rail voltage from where the v tt pin draws load current. there is a limitation between v cc and pv cc . the pv cc voltage must be less or equal to the v cc voltage to ensure the correct output voltage regulation. the v tt source current capability is dependent on pv cc voltage. the higher the voltage on pv cc , the higher the source current. 2 v tt regulator output voltage capable of sinking and sourcing current while regulating the output rail. 3 gnd common ground. 4 /ss suspend shutdown supports suspend to ram function. cmos compatible input sets v tt output to high impedance state. logic hi = enable, logic lo = shutdown. 5 v tts v tts is the v tt sense input. 6 v ref v ref is an output pin that provides the buffered output of the internal reference voltage equal to half of v ddq . two resistors dividing down the v ddq voltage on the pin to create the regulated output voltage. 7 v ddq the v ddq pin is an input pin for creating the internal reference voltage to regulate v tt . the v ddq voltage is connected to an internal resistor divider. the central tap of resistor divider (v ddq /2) is con- nected to the internal voltage buffer, which output is connected to v ref pin and the non ? inverting input of the error amplifier as the reference voltage. 8 v cc power for the analog control circuitry. thermal pad pad for thermal connection. the exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance.
NCP51190 http://onsemi.com 3 absolute maximum ratings rating symbol value unit v cc , pv cc ,v ddq , /ss to gnd (note 1) ? 0.3 to +6 v storage temperature t stg ? 65 to +150 c operating junction temperature range t j ? 40 to +125 c thermal characteristics, so8 ? ep thermal resistance, junction ? to ? air power rating at 25 c ambient r ja tbd c/w esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 150 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. no pin to exceed v cc . refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following method: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) latchup current maximum rating tested per jedec standard: jesd78. recommened operating conditions rating symbol value unit input voltage v cc 2.2 to 5.5 v bias supply voltage pv cc 1.5 to 2.5 v reference input voltage v ddq 1.35 to 2.7 v electrical characteristics ? 40 c t j 125 c; v cc = pv cc = v ddq = 2.5 v; unless otherwise noted. typical values are at t j = +25 c parameter condition symbol min typ max unit reference voltage (ddr i) i ref = 0 ma (unloaded) pv cc = v ddq = 2.3 v = 2.5 v = 2.7 v v ref (ddr ? i) 1.125 1.225 1.325 1.151 1.251 1.351 1.175 1.275 1.375 v reference voltage (ddr ii) i ref = 0 ma (unloaded) pv cc = v ddq = 1.7 v = 1.8 v = 1.9 v v ref (ddr ? ii) 0.830 0.880 0.925 0.851 0.901 0.951 0.880 0.930 0.975 v reference voltage (ddr iii) i ref = 0 ma (unloaded) pv cc = v ddq = 1.35 v = 1.5 v = 1.6 v v ref (ddr ? iii) 0.660 0.735 0.785 0.676 0.751 0.801 0.695 0.770 0.820 v v ref ? output impedance i ref = ? 30 a to +30 a z ref 2.5 k v tt output voltage (ddr ? i) i out = 0 a pv cc = v ddq = 2.3 v pv cc = v ddq = 2.5 v pv cc = v ddq = 2.7 v v tt (ddr ? i) ? 1.112 1.202 1.312 ? 1.150 1.250 1.350 ? 1.182 1.282 1.382 v i out = +1.5 a pv cc = v ddq = 2.3v pv cc = v ddq = 2.5v pv cc = v ddq = 2.7v v tt (ddr ? i) ? 1.115 1.215 1.315 ? 1.150 1.250 1.350 ? 1.185 1.285 1.385 i out = ? 1.5 a pv cc = v ddq = 2.3v pv cc = v ddq = 2.5v pv cc = v ddq = 2.7v v tt (ddr ? i) ? 1.117 1.217 1.317 ? 1.150 1.250 1.350 ? 1.182 1.282 1.382
NCP51190 http://onsemi.com 4 electrical characteristics ? 40 c t j 125 c; v cc = pv cc = v ddq = 2.5 v; unless otherwise noted. typical values are at t j = +25 c parameter unit max typ min symbol condition v tt output voltage (ddr ? ii) i out = 0 a pv cc = v ddq = 1.7 v pv cc = v ddq = 1.8 v pv cc = v ddq = 1.9 v v tt (ddr ? ii) ? 0.816 0.866 0.916 ? 0.850 0.900 0.950 ? 0.881 0.931 0.981 v i out = +0.5 a pv cc = v ddq = 1.7 v pv cc = v ddq = 1.8 v pv cc = v ddq = 1.9 v v tt (ddr ? ii) ? 0.815 0.863 0.914 ? 0.851 0.900 0.950 ? 0.885 0.933 0.984 i out = ? 0.5 a pv cc = v ddq = 1.7 v pv cc = v ddq = 1.8 v pv cc = v ddq = 1.9 v v tt (ddr ? ii) ? 0.814 0.862 0.913 ? 0.850 0.900 0.950 ? 0.884 0.932 0.983 v tt output voltage (ddr ? iii) i out = 0 a p vcc = v ddq = 1.35 v pv cc = v ddq = 1.5 v pv cc = v ddq = 1.6 v v tt (ddr ? iii) ? 0.650 0.725 0.775 ? 0.675 0.750 0.800 ? 0.700 0.775 0.825 v i out = +0.2 a, pv cc = v ddq = 1.35 v i out = ? 0.2 a, pv cc = v ddq = 1.35 v v tt (ddr ? iii) ? 0.649 ? 0.640 ? 0.675 ? 0.675 ? 0.700 ? 0.700 i out = +0.4 a, pv cc = v ddq = 1.5 v i out = ? 0.4 a, pv cc = v ddq = 1.5 v v tt (ddr ? iii) ? 0.722 ? 0.725 ? 0.751 ? 0.750 ? 0.776 ? 0.774 i out = +0.5 a, pv cc = v ddq = 1.6 v i out = ? 0.5 a, pv cc = v ddq = 1.6 v v tt (ddr ? iii) ? 0.773 ? 0.775 ? 0.801 ? 0.800 ? 0.827 ? 0.824 v tt output offset voltage i out = 1.5 a, pv cc = v ddq = 2.5 v v os (ddr ? i) ? 30 0 +30 mv i out = 0.5a, pv cc = v ddq = 1.8v v os (ddr ? ii) ? 30 0 +30 i out = 0.5a, pv cc = v ddq = 1.5v v os (ddr ? iii) ? 30 0 +30 quiescent current i out = 0 a i q 380 500 a v ddq input impedance z vddq 100 k /ss leakage current /ss = 0 v i l_ss 2 5 a quiescent current in suspend shutdown /ss = 0 v i q_ss 115 150 a suspend shutdown threshold v ih 1.9 v v il 0.8 v tt leakage current in suspend shutdown /ss = 0 v, v tt = 1.25 v i l_vtt 1 10 a v tts current i tts 13 na thermal shutdown temperature t sd 165 c thermal shutdown hysteresis t sh 10 c
NCP51190 http://onsemi.com 5 typical performance characteristics figure 2. iq sd vs. v cc figure 3. iq vs. v cc v cc (v) v cc (v) 6 5 4 3 2 0 20 40 60 80 100 120 140 6 5 4 3 2 0 100 200 300 400 500 600 700 figure 4. v ih and v il figure 5. v ref vs. v ddq v cc (v) v ddq (v) 6 5 4 3 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5 4 36 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 figure 6. v tt vs. v ddq figure 7. iq sd vs. v cc over temperature v ddq (v) v cc (v) 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 6 5 4 3 2 0 20 40 60 100 120 140 160 iq sd ( a) iq ( a) ss (v) v ref (v) v tt (v) iq sd ( a) 80 ? 40 c 25 c 85 c 125 c
NCP51190 http://onsemi.com 6 typical performance characteristics figure 8. iq vs. v cc over temperature v cc (v) 6 5 4 3 2 0 100 200 300 500 600 700 800 iq ( a) ? 40 c 25 c 85 c 125 c 400
NCP51190 http://onsemi.com 7 general the NCP51190 is a bus termination, linear regulator designed to meet the jedec requirements for ddr ? i, ddr ? ii and ddr ? iii memory termination. the NCP51190 is capable of sourcing and sinking current while accurately tracking and regulating the v tt output voltage equal to (v ddq / 2). the output stage has been designed to maintain excellent load regulation and preventing shoot ? through. the NCP51190 uses two distinct power rails to separate the analog circuitry from the power output stage and decrease internal power dissipation. supply voltage inputs for added flexibility, separate input pins (v cc and pv cc ) are provided for each required supply input. v cc is used to supply all the internal control circuitry and pv cc is used exclusively to provide the rail voltage for the output stage used to create v tt . these pins have the capability to work off separate supplies with the condition that v cc is always greater than or equal to pv cc , and should always be used with either a 1.8 v or 2.5 v rail. if the junction temperature exceeds the thermal shutdown threshold, the part will enter a shutdown state identical to the manual shutdown where v tt is tri ? stated and v ref remains active. lower voltage rails, such as 1.5 v can be used but will reduce the maximum available output current. generation of internal voltage reference v ddq is the input used to create the internal reference voltage for regulating v tt . the reference voltage is generated from a resistor divider of two internal 50 k resistors. this guarantees that v tt will precisely track (v ddq / 2). the optimal implementation of the v ddq input pin is as a remote sense. this can be achieved by connecting v ddq directly to the 1.8 v rail at the dimm memory module instead of connecting it to pv cc . this ensures that the reference voltage precisely tracks the ddr memory power rail without introducing a large voltage drop due to power traces. for ddr ? ii applications the v ddq input will be 1.8 v, which will create a (v ddq / 2) = 0.9 v termination voltage at the v tt output. v ref provides a buffered output of the internal reference voltage (v ddq / 2). for improved performance, an output bypass capacitor can be placed, close to the pin, to help reduce any potential stray noise. a ceramic capacitor in the range of 0.01 f to 0.1 f is recommended. the v ref output remains active during the shutdown state and thermal shutdown events for the suspend to ram functionality. remote voltage feedback sensing the purpose of the v tts sense pin is to provide improved remote load regulation. in most motherboard applications, the termination resistors will connect to v tt in a long plane. if the output voltage was regulated only at the output of the NCP51190, then any long traces will generate a significant ir drop resulting in a sagging termination voltage at one end of the bus than the other. the v tts pin can be used to improve performance by connecting it to the middle of the bus. this will provide better power distribution across the entire termination bus. if remote load regulation is not used, then the v tts pin must still be connected to v tt . care should be taken when a long v tts trace is implemented in close proximity to the memory. noise pickup in the v tts trace can cause problems with precise regulation of v tt . a small 0.1 f ceramic capacitor placed next to the v tts pin can help filter out any high frequency noise and thereby keeping the v tt power rail in spec. regulator shutdown function the NCP51190 contains an active low enable pin (/ss) that can be used for suspend to ram functionality. in this condition the v tt output will tri ? state, with the v ref output remaining active in order to provide a constant reference signal for the memory and chipset. during shutdown, v tt should not be exposed to voltages that exceed pv cc . with the enable pin asserted low the quiescent current of the NCP51190 will drop, however the v ddq input pin will always draw a constant current due to the integrated 100 k impedance used for generating the internal reference. therefore, to calculate the total power loss in shutdown, both currents need to be considered. the enable pin also has an internal pull ? up current. therefore, to turn the part on, the enable pin can either be connected to v cc or left open. termination voltage output regulation v tt is the regulated output that is used to terminate the bus resistors. it is capable of sourcing and sinking current while regulating the output precisely to v ddq / 2. the NCP51190 is designed to handle continuous currents of up to 1.5 a with excellent load regulation. if a transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor should be sized large enough to prevent an excessive voltage drop. thermal shutdown with hysteresis if the NCP51190 is to operate in elevated temperatures for long durations, care should be taken to ensure that the maximum operating junction temperature is not exceeded. to guarantee safe operation, the NCP51190 provides on ? chip thermal shutdown protection. when the chip junction temperature exceeds 165 c (typical) the part will shutdown. when the junction temperature falls back to 155 c (typical) the device resumes normal operation. if the junction temperature exceeds the thermal shutdown threshold, v tt will tri ? state until the part returns below the temperature hysteresis trip ? point.
NCP51190 http://onsemi.com 8 package dimensions dfn8 2x2, 0.5p case 506aa issue e ?? ?? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view a l (a3) d2 e2 c c 0.10 c 0.10 c 0.08 note 4 a1 seating plane e/2 e 8x k note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k l 0.25 0.35 1 4 8 5 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.50 8x dimensions: millimeters 0.30 pitch 8x 1 package outline recommended l1 detail a l optional constructions l ??? 0.10 0.30 ref 0.90 1.30 on semiconductor and are registered trademar ks of semiconductor components industries, llc (s cillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to an y products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of th e application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products ar e not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action em ployer. this literature is subject to all applicable copyrig ht laws and is not fo r resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP51190/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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